Interrupt Mask Registers 0 To 3 (Imr0 To Imr3) - NEC PD703114 User Manual

V850e/ia2 32-bit single-chip microcontrollers

Table of Contents

7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)

These registers set the interrupt mask state for the maskable interrupts.

The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn bit of the xxICn register.

IMRm can be read/written in 16-bit units (m = 0 to 3).

When the IMRm register is divided into two registers: higher 8 bits (IMRmH register) and lower 8 bits (IMRmL

Caution The device file defines the xxMKn bit of the xxICn register as a reserved word. If a bit is

manipulated with the name xxMKn, therefore, the xxICn register, rather than the IMRm register, is

rewritten (as a result, the IMRm register is also rewritten).

Bit position

15 to 7, 4 to 0 (IMR0)

15 to 5, 0 (IMR1)

15 to 9, 4 to 0 (IMR2)

13 to 7, 3, 2 (IMR3)

Remark xx: Identification name of each peripheral unit (refer to Table 7-2).

n: Peripheral unit number (refer Table 7-2)

CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION

Interrupt mask flag

0: Interrupt servicing enabled

1: Interrupt servicing disabled (pending)

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