Table 11-6: Counter Clear Operation - NEC V850E/PH2 User Manual

Operation Mode
Interval mode
External event count mode
External trigger pulse output mode Compare match
One-shot pulse mode
PWM mode
Free-running mode
Pulse width measurement mode
Triangular wave PWM mode
Encoder compare mode
Offset trigger generation mode
Note: Conditions are set with bits TTnECM0 and TTnECM1 of the TTnCTL2 register.
(3) Counter reset and hold operations
In the encoder compare mode, counter value hold is controlled with bit TTnECC of the TTnCTL2
register.
If TTnCE = 0 is set when TTnECC = 0, the counter is reset to 0000H. The setting value of the
TTnTCW register is loaded to the counter when TTnCE = 1 is set next.
If TTnCE = 0 is set when TTnECC = 1, the counter value is held as is. Counting resumes from the
held value when TTnCE = 1 is set next.
(4) Counter read operation during counter operation
In TMT, the counter value can be read during count operation using the TTnCNT register.
Remark: n = 0, 1
Chapter 11 16-bit Timer/Event Counter T

Table 11-6: Counter Clear Operation

TTnCCR0
Compare match
Compare match
Compare match
Compare match
-
-
Compare match
Depends on set
Note
conditions
-
User's Manual U16580EE3V1UD00
Clear Cause
TTnCCR1
-
-
-
-
-
-
-
-
Depends on set
Note
conditions
-
Other
-
-
External trigger (TTRGTn
pin)
-
-
-
External input (TITn0 and
TITn1 pins)
-
Pin TECRTn, clear
condition level match
External input (TITn0 pin)
481