Interrupt Mask Registers 0 To 3 (Imr0 To Imr3) - NEC V850E/IA1 mPD703116 User Manual

7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)

These registers set the interrupt mask state for the maskable interrupts.
The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn bit of the xxICn register.
IMRm can be read/written in 16-bit units (m = 0 to 3).
When the IMRm register is divided into two registers: higher 8 bits (IMRmH register) and lower 8 bits (IMRmL
register), these registers can be read/written in 8-bit or 1-bit units.
Caution The device file defines the xxMKn bit of the xxICn register as a reserved word. If a bit is
manipulated with the name xxMKn, therefore, the xxICn register, rather than the IMRm register,
is rewritten (as a result, the IMRm register is also rewritten).
<15> <14>
IMR0 CM10MK0 CC10MK1
<7> <6>
DETMK0 P0MK6
<15> <14>
IMR1 CC3MK1 CC3MK0
<7> <6>
CC2MK0 TM2MK1
<15> <14>
IMR2 STMK1 SRMK1
<7> <6>
CANMK2 CANMK1
15 14
IMR3 1 1
7 6
1 1
Bit Position Bit Name
15 to 0 xxMKn
(IMR0 to 2),
0 to 3 (IMR3)
Remark xx: Identification name of each peripheral unit (refer to Table 7-2)
n: Peripheral unit number (refer to Table 7-2)
182
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
<13> <12> <11>
CC10MK0 CM03MK1 TM0MK1
<5> <4> <3>
P0MK5 P0MK4 P0MK3
<13> <12> <11>
TM3MK0 CC2MK5 CC2MK4
<5> <4> <3>
TM2MK0 CM11MK1 CM11MK0
<13> <12> <11>
SEMK0 STMK0 SRMK0
<5> <4> <3>
CANMK0 DMAMK3 DMAMK2
13 12 11
1 1 1
5 4 <3>
1 1 ADMK1
Interrupt mask flag
0: Interrupt servicing enabled
1: Interrupt servicing disabled (pending)
User's Manual U14492EJ3V0UD
<10> <9> <8>
CM03MK0 TM0MK0 DETMK1
<2> <1> <0>
P0MK2 P0MK1 P0MK0
<10> <9> <8>
CC2MK3 CC2MK2 CC2MK1
<2> <1> <0>
CC11MK1 CC11MK0 CM10MK1
<10> <9> <8>
CSIMK1 CSIMK0 CANMK3
<2> <1> <0>
DMAMK1 DMAMK0 CM4MK0
10 9 8
1 1 1
<2> <1> <0>
ADMK0 STMK2 SRMK2
Function
Address Initial value
FFFFF100H FFFFH
Address Initial value
FFFFF102H FFFFH
Address Initial value
FFFFF104H FFFFH
Address Initial value
FFFFF106H FFFFH