Figure 12-22: Example Of Tm1Operation In Udc Mode - NEC V850E/PH2 User Manual

Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10)
(c) Compare function
TM1n connects two compare register (CM100, CM101) channels and two capture/compare
register (CC100, CC101) channels.
When the TMENC10 count value and the set value of one of the compare registers match, a
match interrupt (INTCM10, INTCM11, INTCC10
Note: This match interrupt is generated when CC100 and CC101 are set to the compare register
mode.
(d) Capture function
TMENC10 connects two capture/compare register (CC100, CC101) channels.
When CC100 and CC101 are set to the capture register mode, the value of TMENC10 is captured
in synchronization with the corresponding capture trigger signal.
When the TMENC10 is set to the capture register mode, a capture interrupt (INTCC10, INTCC11)
is generated upon detection of the valid edge.
(4) Operation in UDC mode B
(a) Basic operation
The operations at the next count clock after the count value of TMENC10 and the CM100 set value
match when TMENC10 is in UDC mode B are as follows.
• In case of up count operation:
• In case of down count operation: The TMENC10 count value is decremented (-1).
The operations at the next count clock after the count value of TMENC10 and the CM101 set value
match when TMENC10 is in UDC mode B are as follows.
• In case of up count operation:
• In case of down count operation: TMENC10 is cleared (0000H) and the INTCM11 interrupt is
CM10 set value
TMENC1 count value
CM11 set value
564
TMENC10 is cleared (0000H) and the INTCM10 interrupt is
generated.
The TMENC10 count value is incremented (+1).
generated.

Figure 12-22: Example of TM1Operation in UDC Mode

Clear
cleared if count clock
counts down following match
User's Manual U16580EE3V1UD00
Note
, INTCC11
TMENC1 not
Note
) is output.
TMENC1 not
cleared if count clock
Clear counts up following match