Figure 7-17: Interrupt Mode Register 2 (Intm2) - NEC V850E/PH2 User Manual

(3) Interrupt mode register 2 (INTM2)
The behaviour of the external interrupt input pins INTP7 to INTP10 can be specified by the
interrupt mode register 2 (INTM2).
The INTM2 register can be read/written in 8-bit or 1-bit units.
After reset: 00H
7
INTM1 ES101
ES101
0
0
1
1
ES91
0
0
1
1
ES81
0
0
1
1
ES71
0
0
1
1
Caution: Changing the state of interrupt mode configuration registers ESn0/ESn1 may trigger
an unintended interrupt event for the respective interrupt channels. Be sure to mask
the respective interrupt channel and clear the interrupt status flag after changing the
bits ESn0/ESn1 of the interrupt channel (n = 7 to 10).
Chapter 7 Interrupt/Exception Processing Function

Figure 7-17: Interrupt Mode Register 2 (INTM2)

R/W
6 5
ES100 ES91
ES100
0 Falling edge
1 Rising edge
0 Setting prohibited
1 Both, rising and falling edges
ES90
0 Falling edge
1 Rising edge
0 Setting prohibited
1 Both, rising and falling edges
ES80
0 Falling edge
1 Rising edge
0 Setting prohibited
1 Both, rising and falling edges
ES70
0 Falling edge
1 Rising edge
0 Setting prohibited
1 Both, rising and falling edges
User's Manual U16580EE3V1UD00
Address: FFFFF884H
4 3
ES90 ES81
Valid Edge Specification of INTP10 pin input
Valid Edge Specification of INTP9 pin input
Valid Edge Specification of INTP8 pin input
Valid Edge Specification of INTP7 pin input
2 1
ES80 ES71 ES70
0
247