Table 6-3: Dma Configuration Of Serial Data Transmission - NEC V850E/PH2 User Manual

(2) Serial data transmission with DMA transfer
The DMAC has two dedicated channels (6 and 7) to support the serial data transmission. Each of
both channels can be assigned to a serial interface (CSI30, CSI31
UARTC0, UARTC1). As DMA trigger factor, which requests and starts the DMA transfer, the corre-
sponding transmission enable interrupt signal is pre-defined (refer to Table 6-3).
For each DMA trigger the data will be transferred from internal RAM to the corresponding serial
transmit register. Depending on the serial interface the transfer data size can be set to 8 or 16 bits
(refer to Table 6-3).
In case of 8 bits transfer data size, the source address is incremented by 1 for each occurrence of
DMA trigger. When selecting 16 bits transfer data size the source address must be even, and is
incremented by 2 for each DMA trigger.
When the DMA transfer count of a DMA channel terminates, the DMA transfer is stopped and a
DMA completion interrupt is generated. The maximum DMA transfer count is 256.

Table 6-3: DMA Configuration of Serial Data Transmission

Serial Interface DMA Trigger
Note 2
CSI30
Notes 1, 2
CSI31
CSIB0
Note 1
CSIB1
UARTC0 INTUC0T
UARTC1 INTUC1T
Notes: 1. Not available on μPD70F3447.
2. The serial peripheral chip select lines SCS0 to SCS3 will not be supported by DMA transfer.
212
Chapter 6 DMA Functions (DMA Controller)
Transfer Data
Factor Size
INTC30 8 bits
16 bits
INTC31 8 bits
16 bits
INTCB0T 8 bits
16 bits
INTCB1T 8 bits
16 bits
8 bits
16 bits
8 bits
16 bits
User's Manual U16580EE3V1UD00
Source
Any iRAM address
Any even iRAM address
Any iRAM address
Any even iRAM address
Any iRAM address
Any even iRAM address
Any iRAM address
Any even iRAM address
Any iRAM address
Setting prohibited
Any iRAM address
Setting prohibited
Note 1
, CSIB0, CSIB1
Destination
SFDB0L
SFDB0
SFDB1L
SFDB1
CB0TXL
CB0TX
CB1TXL
CB1TX
UC0TX
UC1TX
Note 1
,