3.4.11 Cautions
•
Initialize the following registers immediately after reset signal release in the following sequence:
- System wait control register (VSWC)
(refer to 3.4.9
System wait control register (VSWC))
- DMA wait control registers 0 and 1 (DMAWC0,DMAWC1)
(refer to 3.4.10
Chapter 3 CPU Functions
DMA wait control registers 0 and 1 (DMAWC0, DMAWC1))
User's Manual U16580EE3V1UD00
143