Output Pins; Table 17-3: Default Output Level Of Sck3N Pin; Table 17-4: Default Output Level Of So3N Pin - NEC V850E/PH2 User Manual

17.5.16 Output pins

(1) SCK3n pin
The SCK3n pin outputs a high level when both the CTXEn and CRXEn bits of the CSIM3n register
are 0 (n = 0, 1).
In the master mode (CKS3n2 to CKS3n0 bits = other than 111 in the CSIC3n register), this pin
outputs the default level when the FPCLRn bit of the SFA3n register is set to 1.
In the slave mode (CKS3n2 to CKS3n0 bits = 111 in the CSIC3n register), the default output level
of the SCK3n pin is fixed to the high level.
CKPn Bit
0
1
Note: Default value after reset, or value when CSICAEn bit of the CSIM3n register is cleared to 0.
Remarks: 1. The output of the SCK3n pin changes if the CKPn bit is rewritten in the master mode.
2. μPD70F3187:
μPD70F3447:
(2) SO3n pin
The SO3n pin outputs a low level when both the CTXEn and CRXEn bits of the CSIM3n register
are 0 (n = 0, 1).
This pin outputs a low level when the FPCLRn bit of the SFA3n register is set to 1 (the previous
value is retained only in the slave mode (CKS3n2 to CKS3n0 bits of the CSIC3n register = 111B)
and when the DAPn bit of the CSIC3n register is 0).
Note
Low level
Note: Default value after reset, or value when CSICAEn bit of the CSIM3n register is cleared to 0
μPD70F3187:
Remark:
μPD70F3447:
712
Chapter 17 Clocked Serial Interface 3 (CSI3)

Table 17-3: Default Output Level of SCK3n Pin

CKS3n2 to CKS3n0 Bits
111B (slave mode)
Other than 111B (master mode)
111B (slave mode)
Other than 111B (master mode)
n = 0, 1
n = 0

Table 17-4: Default Output Level of SO3n Pin

Default Output Level of SO3n Pin
n = 0, 1
n = 0
User's Manual U16580EE3V1UD00
Default Output Level of SCK3n Pin
Note
High level
High level
High level
Low level