Consecutive Mode - NEC V850E/PH2 User Manual

17.5.10 Consecutive mode

The consecutive mode is set when the TRMDn bit of the CSIM3n register is 1 (μPD70F3187: n = 0, 1,
μPD70F3447: n = 0).
In this mode, transfer is started when the CTXEn bit or CRXEn bit is 1 and when data is in the CSIBUFn
register (SFEMPn bit of the SFA3n register = 0). At this time, set the number of transfer data in advance
by using the SFNn3 to SFNn0 bits of the SFN3n register. Seventeen or more transfer data cannot be
set. If 17 or more transfer data are written to the CSIBUFn register, the excess data are ignored and not
transferred. Do not write data exceeding the number of transfer data specified by the SFNn3 to SFNn0
bits of the SFN3n register to the CSIBUFn register.
If no data is in the CSIBUFn register (SFEMPn bit = 1), transfer is kept waiting until a given start
condition is satisfied.
If data is written to the CSIBUFn register when the CTXEn or CRXEn bit is 1, the CSOTn bit (transfer
status flag) of the SFA3n register is set to 1 and the chip select data (CS data) according to the SIO3n
load/store CSIBUFn pointer is transferred to the chip select output buffer. However, in slave mode
(CKS3n2 to CKS3n0 bits of the CSIC3n register = 111B) the chip select outputs (SCS3n0 to SCS3n3)
keep always the inactive level.
If transfer is not in the wait status, the transfer data indicated by the SIO3n load/store CSIBUFn pointer
is loaded from the CSIBUFn register to SIO3n register. Then transfer processing is started.
When transfer processing of one data is completed in the reception mode or transmission/reception
mode, the received data is overwritten from the SIO3n register to the transfer data in the CSIBUFn
register indicated by the SIO3n load/store CSIBUFn pointer, and then the pointer is incremented. By
consecutively reading the transfer data from the SIRB3n register after all data in the CSIBUFn register
have been transferred (when the INTC3n interrupt has occurred), the receive data can be sequentially
read while the read CSIBUFn pointer is incremented.
In the transmission mode, the SIO3n load/store CSIBUFn pointer is incremented when transfer
processing of one data has been completed.
In all modes (transmission, reception, and transmission/reception modes), when data has been
transferred by the value set by the SFNn3 to SFNn0 bits of the SFN3n register, the CSOTn bit is cleared
to 0 and the transmission/reception completion interrupt (INTC3n) is output.
To transfer the next data, be sure to write 1 to the FPCLRn bit of the SFA3n register and clear all the
CSIBUFn pointers to 0.
The "number of transferred data (SIO3n load/store CSIBUFn pointer value)" can always be read from
the SFPn3 to SFPn0 bits of the SFA3n register.
Caution: The SFA3n register is in the same status when transfer data is written (before start of
transfer) after the CSIBUFn pointer is cleared (FPCLRn bit of the SFA3n register = 1)
and when 16 data have been transferred (SFFULn bit = 0, SFEMPn bit = 1, SFPn3 to
SFPn0 bits = 0000B).
Chapter 17 Clocked Serial Interface 3 (CSI3)
User's Manual U16580EE3V1UD00 705