Interrupt Control Register (Picn); Figure 7-10: Interrupt Control Register (Picn) - NEC V850E/PH2 User Manual

7.3.4 Interrupt control register (PICn)

An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the
control conditions for each maskable interrupt request.
This register can be read/written in 8-bit or 1-bit units.
After reset: 47H
7
PICn IFn
IFn
0
1
MKn
0
1
PRn2
0
0
0
0
1
1
1
1
Note: Automatically reset by hardware when interrupt request is acknowledged.
Remark: n = 0 to 105 (see Table 7-2:
236
Chapter 7 Interrupt/Exception Processing Function

Figure 7-10: Interrupt Control Register (PICn)

R/W
6 5
MKn 0
Interrupt request is not issued
Interrupt request issued
Interrupt servicing enabled
Interrupt servicing disabled (IFn flag hold pending)
PRn1 PRn0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Addresses and Bits of Interrupt Control Registers)
User's Manual U16580EE3V1UD00
Address: Refer to Table 7-2
4 3
0 0
Interrupt Request Flag n
Interrupt Mask Flag n
Interrupt Priority Specification n
Specifies level 0 (highest)
Specifies level 1
Specifies level 2
Specifies level 3
Specifies level 4
Specifies level 5
Specifies level 6
Specifies level 7 (lowest)
2 1
PRn2 PRn1 PRn0
Note
0