Pwm Mode (Tpnmd2 To Tpnmd0 = 100B) - NEC V850E/PH2 User Manual

Chapter 9 16-Bit Timer/Event Counter P

9.5.6 PWM mode (TPnMD2 to TPnMD0 = 100B)

In the PWM mode, TMPn capture/compare register 1 (TPnCCR1) is used as the duty setting register
and TMPn capture/compare register 0 (TPnCCR0) is used as the cycle setting register.
Variable duty PWM is output by setting these two registers and operating the timer.
The TPnCCR0 register and the TPnCCR1 register can be rewritten when TPnCE = 1.
In order for the setting value when the TPnCCR0 register and the TPnCCR1 register are rewritten to
become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to
CCR0 buffer register or CCR1 buffer register), it is necessary to rewrite TPnCCR0 and then write to the
TPnCCR1 register before the 16-bit counter value and the TPnCCR0 register value match. Thereafter,
the values of the TPnCCR0 register and the TPnCCR1 register are reloaded upon a TPnCCR0 register
match.
Whether to enable or disable the next reload timing is controlled by writing to the TPnCCR1 register.
Thus even when wishing only to rewrite the value of the TPnCCR0 register, also write the same value to
the TPnCCR1 register.
Reload is disabled even when only the TPnCCR0 register is rewritten. To stop timer P, set TPnCE = 0.
Note
PWM waveform output is performed from the TOPn1 pin. The TOPn0 pin performs toggle output
upon a match between the 16-bit counter and the TPnCCR0 register.
Since the TPnCCR0 and TPnCCR1 registers have their function fixed that of a compare register in the
PWM mode, they cannot be used for capture operation in this mode.
Note: TOPn0 output pin is not available for TMP8 (n = 8).
Remark: n = 0 to 8
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