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Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10)
(3)
Compare register 101 (CM101)
CM101 is a 16-bit register that always compares its value with the value of TMENC10. When the
value of a compare register matches the value of TMENC10, an interrupt signal is generated. The
interrupt generation timing in the various modes is described below.
• In the general-purpose timer mode (CMD bit of TUM10 register = 0) and UDC mode A (MSEL
bit of TUM10 register = 0), an interrupt signal (INTCM11) is always generated upon occurrence
of a match.
• In UDC mode B (MSEL bit of TUMn register = 1), an interrupt signal (INTCM11) is generated
only upon occurrence of a match during down count operation.
This register can be read/written in 16-bit units.
Reset input clears this register to 0000H.
Caution:
When the TM1CE bit of the TMC10 register is 1, it is prohibited to overwrite the value
of the CM101 register.
After reset:
15
14
CM101
542
Figure 12-4: Compare Register 101 (CM101)
0000H
R/W
13
12
11
10
User's Manual U16580EE3V1UD00
Address:
FFFFF6B4H
9
8
7
6
5
4
3
2
1
0
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