NEC V850E/PH2 User Manual page 26

Figure 20-67: Port Register DH(PDH)
Figure 20-68: Port Mode Register DH(PMDH)
Figure 20-69: Port Mode Control Register DH (PMCDH)
Figure 20-70: Port Register CS (PCS) ........................................................................................... 953
Figure 20-71: Port Mode Register CS (PMCS) ............................................................................... 954
Figure 20-72: Port Mode Control Register CS (PMCCS) ............................................................... 954
Figure 20-73: Port Register CT (PCT) ........................................................................................... 955
Figure 20-74: Port Mode Register CT (PMCT) ............................................................................... 956
Figure 20-75: Port Mode Control Register CT (PMCCT) ............................................................... 957
Figure 20-76: Port Register CM (PCM) .......................................................................................... 958
Figure 20-77: Port Mode Register CM (PMCM) .............................................................................. 959
Figure 20-78: Port Mode Control Register CM (PMCCM) .............................................................. 960
Figure 20-79: Port Register CD (PCD) .......................................................................................... 961
Figure 20-80: Port Mode Register CD (PMCD) .............................................................................. 963
Figure 20-81: Port Mode Control Register CD (PMCCD) .............................................................. 964
Figure 20-82: Noise Elimination Control Register (NRC) (1/2) ....................................................... 967
Figure 21-1: Reset Timing ............................................................................................................. 972
Figure 22-1: Internal RAM Parity Error Status Register (RAMERR) ............................................ 974
Figure 22-2: Internal RAM Parity Error Address Register (RAMPADD) ...................................... 975
Figure 23-1: Connecting N-Wire Type Emulator (IE-V850E1-CD-NW (N-Wire Card)) .................. 979
Figure 23-2: Pin Configuration of Emulator Connector (on Target System Side) .......................... 980
Figure 23-3: Example of Recommended Emulator Connection of V850E/PH2............................. 982
Flash Memory Mapping of μPD70F3187................................................................... 986
Figure 24-1:
Flash Memory Mapping of μPD70F3447................................................................... 987
Figure 24-2:
Figure 24-3: Environment Required for Writing Programs to Flash Memory ................................. 991
Figure 24-4: Communication with Dedicated Flash Programmer (UARTC0) ................................ 992
Figure 24-5: Communication with Dedicated Flash Programmer (CSIB0) .................................... 992
Figure 24-6: Communication with Dedicated Flash Programmer (CSIB0 + HS) ........................... 993
Figure 24-7: Procedure for Manipulating Flash Memory................................................................ 995
Figure 24-8: Selection of Communication Mode............................................................................ 996
Figure 24-9: Communication Commands ...................................................................................... 997
Figure 24-10: FLMD0 Pin Connection Example .............................................................................. 998
Figure 24-11: FLMD1 Pin Connection Example .............................................................................. 999
Figure 24-12: Conflict of Signals (Serial Interface Input Pin) ......................................................... 1000
Figure 24-13: Malfunction of Other Device .................................................................................... 1001
Figure 24-14: Conflict of Signals (RESET Pin) .............................................................................. 1002
Figure 24-15: Concept of Self Programming ................................................................................. 1003
Figure 24-16: Rewriting Entire Memory Area (Boot Swap)............................................................ 1005
Figure 25-1: Oscillator Recommendations................................................................................... 1009
Figure 25-2: AC Test Input/Output Waveform ............................................................................. 1011
Figure 25-3: AC Test Load Condition .......................................................................................... 1011
Figure 25-4: External Asynchronous Memory Access Read Timing............................................ 1013
Figure 25-5: External Asynchronous Memory Access Write Timing............................................ 1015
Figure 25-6: Reset Timing ........................................................................................................... 1016
Figure 25-7: Interrupt Timing ....................................................................................................... 1017
Figure 25-8: Timer P Characteristics ........................................................................................... 1018
Figure 25-9: Timer R Characteristics ........................................................................................... 1019
Figure 25-10: Timer T Characteristics ........................................................................................... 1020
Figure 25-11: CSIB Timing in Master Mode (CKP, DAP bits = 00B or 11B).................................. 1022
Figure 25-12: CSIB Timing in Master Mode (CKP, DAP bits = 01B or 10B).................................. 1022
Figure 25-13: CSIB Timing in Slave Mode (CKP, DAP bits = 00B or 11B).................................... 1023
Figure 25-14: CSIB Timing in Slave Mode (CKP, DAP bits = 01B or 10B).................................... 1023
Figure 25-15: CSI3 Timing in Master Mode (CKP, DAP bits = 00B or 11B) .................................. 1025
Figure 25-16: CSI3 Timing in Master Mode (CKP, DAP bits = 01B or 10B) .................................. 1025
Figure 25-17: CSI3 Timing in Slave Mode (CKP, DAP bits = 00B or 11B) .................................... 1026
Figure 25-18: CSI3 Timing in Slave Mode (CKP, DAP bits = 01B or 10B) .................................... 1026
Figure 25-19: CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 0, CSMD = 0) .. 1027
Figure 25-20: CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 1, CSMD = 0) .. 1027
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User's Manual U16580EE3V1UD00
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