Non-Maskable Interrupt - NEC V850E/PH2 User Manual

Chapter 7 Interrupt/Exception Processing Function

7.2 Non-maskable Interrupt

A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the
interrupt disabled (DI) status. A NMI is not subject to priority control and takes precedence over all the
other interrupts.
A non-maskable interrupt request is input from the NMI pin. When the valid edge specified by ESN0,
ESN1 bits of the interrupt mode register 0 (INTM0) is detected at the NMI pin, the interrupt occurs.
While the service program of the non-maskable interrupt is being executed (PSW.NP = 1), the
acknowledgment of another non-maskable interrupt request is held pending. The pending NMI is
acknowledged after the original service program of the non-maskable interrupt under execution has
been terminated (by the RETI instruction). Note that if two or more NMI requests are input during the
execution of the service program for a NMI, the number of NMIs that will be acknowledged after
PSW.NP is cleared to 0 is only one.
Remark: PSW.NP: The NP bit of the PSW register.
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