Sbf Receive Operation; Figure 15-15: Sbf Reception Timing - NEC V850E/PH2 User Manual

15.5.4 SBF receive operation

The reception enabled status is achieved by setting the UCnPWR bit of the UCnCTL0 register to 1 and
then setting the UCnRX bit of the UCnCTL0 register to 1.
The SBF reception wait status is set by setting the SBF reception trigger (UCnSRT bit of the UCnOPT0
register) to 1.
In the SBF reception wait status, similarly to the UART reception wait status, the RXDCn pin is
monitored and start bit detection is performed.
Following detection of the start bit, reception is started and the internal counter counts up according to
the set baud rate.
When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a
reception complete interrupt (INTUCnR) is output. Error detection for the UCnOVE, UCnPE, and
UCnFE bits of the UCnSTR register is suppressed and UART communication error detection
processing is not performed. Moreover, UARTCn reception shift register and data transfer of the
UCnRX register are not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer bits,
reception is terminated as error processing without outputting an interrupt, and the SBF reception mode
is returned to. The UCnSRF bit is not cleared at this time.
(a) Normal SBF reception (detection of stop bit in more than 10.5 bits)
UCnSRF
INTUCnR
interrupt
(b) SBF reception error (detection of stop bit in 10.5 or fewer bits)
UCnSRF
INTUCnR
interrupt
Chapter 15 Asynchronous Serial Interface C (UARTC)

Figure 15-15: SBF Reception Timing

1 2 3
1 2
User's Manual U16580EE3V1UD00
4 5 6 7 8
11.5
3 4 5 6 7
10.5
9 10 11
8 9 10
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