NEC V850E/PH2 User Manual page 22

Figure 14-3: A/D Converter n Mode Register 1 (ADMn1) (1/2) ..................................................... 577
Figure 14-4: A/D Converter n Mode Register 2 (ADMn2) ............................................................ 579
Figure 14-5: A/D Converter n Trigger Source Select Register (ADTRSELn) ............................... 580
Figure 14-6: A/D Conversion Result Registers n0 to n9, n0H to n9H
(ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) ..................................................... 581
Figure 14-7: Relationship Between Analog Input Voltage and A/D Conversion Results ............... 583
Figure 14-8: A/D Conversion Result Registers n0 to n9, n0H to n9H
(ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) ..................................................... 584
Figure 14-9: Select Mode Operation Timing: 1-Buffer Mode (ANIn1)............................................ 588
Figure 14-10: Select Mode Operation Timing: 4-Buffer Mode (ANIn2)............................................ 589
Figure 14-11: Scan Mode Operation Timing: 4-Channel Scan (ANI0 to ANI3)................................ 590
Figure 14-12: Example of 1-Buffer Mode Operation (A/D Trigger Select: 1 Buffer)......................... 591
Figure 14-13: Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers)....................... 593
Figure 14-14: Example of Scan Mode Operation (A/D Trigger Scan).............................................. 595
Figure 14-15: Example of 1-Buffer Mode Operation (Timer Trigger Select: 1 Buffer) (ANIn1) ........ 597
Figure 14-16: Example of 4-Buffer Mode Operation (Timer Trigger Select: 4 Buffers) (ANIn3) ...... 599
Figure 14-17: Example of Scan Mode Operation (Timer Trigger Scan) (ANIn0 to ANIn4) .............. 601
Figure 14-18: Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer) (ANIn1) .... 603
Figure 14-19: Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers) (ANIn2) .. 605
Figure 14-20: Example of Scan Mode Operation (External Trigger Scan) (ANIn0 to ANIn3) .......... 607
Figure 15-1: Block Diagram of Asynchronous Serial Interface n ................................................... 611
Figure 15-2: UARTCn Control Register 0 (UCnCTL0) (1/2) ........................................................ 612
Figure 15-3: UARTCn Control Register 1 (UCnCTL1) ................................................................. 614
Figure 15-4: UARTCn Control Register 2 (UCnCTL2) ................................................................. 615
Figure 15-5: UARTCn Option Control Register 0 (UCnOPT0) (1/2) ............................................. 616
Figure 15-6: UARTCn Option Control Register 1 (UCnOPT1) ..................................................... 618
Figure 15-7: UARTCn Status Register (UCnSTR) (1/2) .............................................................. 620
Figure 15-8: UARTCn Status Register 1 (UCnSTR1) .................................................................. 622
Figure 15-9: UARTCn Receive Data Register (UCnRX, UCnRXL) .............................................. 623
Figure 15-10: UARTCn Transmit Data Register (UCnTX, UCnTXL) .............................................. 624
Figure 15-11: UARTC Transmit/Receive Data Format (1/2)............................................................ 626
Figure 15-12: LIN Transmission Manipulation Outline..................................................................... 628
Figure 15-13: LIN Reception Manipulation Outline .......................................................................... 629
Figure 15-14: SBF Transmission Timing ......................................................................................... 630
Figure 15-15: SBF Reception Timing............................................................................................... 631
Figure 15-16: UART Transmission .................................................................................................. 632
Figure 15-17: Continuous Transmission Processing Flow............................................................... 633
Figure 15-18: Continuous Transfer Operation Timing ..................................................................... 634
Figure 15-19: UART Reception Timing............................................................................................ 635
Figure 15-20: Noise Filter Circuit ..................................................................................................... 638
Figure 15-21: Configuration of Baud Rate Generator ...................................................................... 639
Figure 15-22: Allowable Baud Rate Range During Reception......................................................... 642
Figure 15-23: Transfer Rate During Continuous Transfer ............................................................... 644
Figure 16-1: Block Diagram of CSIBn............................................................................................ 646
Figure 16-2: CSIBn Receive Data Register (CBnRX, CBnRXL) ................................................... 647
Figure 16-3: CSIBn Transmit Data Register (CBnTX, CBnTXL) ................................................... 648
Figure 16-4: CSIBn Control Register 0 (CBnCTL0) (1/2) ............................................................. 649
Figure 16-5: CSIBn Control Register 1 (CBnCTL1) ..................................................................... 651
Figure 16-6: CSIBn Control Register 2 (CBnCTL2) ...................................................................... 652
Figure 16-7: Effect of Transfer Data Length Setting ...................................................................... 653
Figure 16-8: CSIBn Status Register (CBnSTR) ........................................................................... 654
Figure 16-9: Single Transfer Mode (Master Mode, Transmission/Reception Mode) ..................... 655
Figure 16-10: Single Transfer Mode (Master Mode, Transmission Mode) ...................................... 656
Figure 16-11: Single Transfer Mode (Master Mode, Reception Mode)............................................ 657
Figure 16-12: Continuous Mode (Master Mode, Transmission/Reception Mode) ........................... 658
Figure 16-13: Continuous Mode (Master Mode, Transmission Mode)............................................. 659
Figure 16-14: Continuous Mode (Master Mode, Reception Mode).................................................. 660
Figure 16-15: Continuous Reception Mode (Error).......................................................................... 661
22 User's Manual U16580EE3V1UD00