NEC V850E/PH2 User Manual page 735

<1> When the CSICAEn bit of the CSIM3n register is set to 1, operating clock supply is enabled.
<2> Specify the transfer mode by setting the CSIC3n and CSIL3n registers.
<3> Write 1 to the FPCLRn bit of the SFA3n register to clear all the CSIBUFn pointers to 0.
<4> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n
register.
<5> Specify the transfer mode by using the TRMDn, DIRn, CSITn, CSWEn, and CSMDn bits of the
CSIM3n register and, at the same time, enable reception by setting the CRXEn bit to 1.
<6> Set the number of data to be received by using the SFNn3 to SFNn0 bits of the SFN3n register.
<7> Write dummy transfer data to the SFDB3n register (reception start trigger). Writing dummy data
exceeding the set value of the SFN3n register is prohibited.
Since the chip select outputs (SCS3n0 to SCS3n3) are ineffective in the slave mode and always
output the inactive level, writing of CS data to the SFCS3n register is not necessary.
<8> Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1. Then read the SIRB3n
register (sequentially read the receive data stored in the CSIBUFn register).
<9> Write 1 to the FPCLRn bit of the SFA3n register, and clear all the CSIBUFn pointers to 0 in
preparation for the next transfer.
<10> Confirm that the SFFULn bit = 0, SFEMPn bit = 1, and SFPn3 to SFPn0 bits = 0000 in the SFA3n
register.
<11> Disable reception by clearing the CRXEn bit of the CSIM3n register to 0 (end of reception).
Remarks: 1. To execute a further transfer, repeat <6> to <10> before <11>.
Perform writing dummy transfer data in <7> every time transfer is executed.
2. The SO3n pin output is fixed to low level (default value).
3. μPD70F3187:
μPD70F3447:
Chapter 17 Clocked Serial Interface 3 (CSI3)
n = 0, 1
n = 0
User's Manual U16580EE3V1UD00 735