Figure 11-12: Tmtn I/O Control Register 3 (Ttnioc3) (1/2) - NEC V850E/PH2 User Manual

(7) TMTn I/O control register 3 (TTnIOC3)
The TTnIOC3 register is an 8-bit register that controls the valid edge of encoder clear input
(TECRTn pin) and encoder input (TENCTn1 and TENCTn0 pins).
This register can be read and written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Set the TTnIOC3 register when TTnCE = 0. When TTnCE = 1, write access to the TTnIOC2
register can be performed using the same value.

Figure 11-12: TMTn I/O Control Register 3 (TTnIOC3) (1/2)

After reset: 00H
7
TTnIOC3 TTnSCE
(n = 0, 1)
TTnSCE
0
1
When TTnSCE = 1, the counter is cleared to 0000H if all the conditions set with bits
TTnZCL, TTnBCL, and TTnACL are matched.
When TTnSCE = 1, the settings of bits TTnECS1 and TTnECS0 are invalid, so no encoder
clear interrupt (INTTTnEC) is output.
When TTnSCE = 0, the settings of bits TTnZCL, TTnBCL, and TTnACL are invalid. The
settings of bits TTnECS1 and TTnECS0 become valid, and the encoder clear interrupt
(INTTTnEC) is output.
Caution: When TTnSCE = 1, be sure to set bits TTnUDS1, and TTnUDS0 of the
TTnZCL
0
1
Remark: The TTnZCL bit is valid when TTnSCE = 1.
TTnBCL
0
1
Remark: The TTnBCL bit is valid when TTnSCE = 1.
TTnACL
0
1
Remark: The TTnACL bit is valid when TTnSCE = 1.
Remark: n = 0, 1
474
Chapter 11 16-bit Timer/Event Counter T
R/W Address:
6 5
TTnZCL TTnBCL
Selects the encoder counter clear method
Clear upon detection of edge of TECRTn pin
Clear upon match of clear condition level
TTnCTL2 register to 10B or 11B.
Sets the clear level for the Z phase of encoder input (TECRTn pin)
Clear condition = Low level
Clear condition = High level
Sets the clear level for the B phase of encoder input (TENCTn1 pin)
Clear condition = Low level
Clear condition = High level
Sets the clear level for the A phase of encoder input (TENCTn0 pin)
Clear condition = Low level
Clear condition = High level
User's Manual U16580EE3V1UD00
TT0IOC3 FFFFF696H,
TT1IOC3 FFFFF6A6H
4 3
TTnACL TTnECS1 TTnECS0 TTnEIS1
2 1 0
TTnEIS0