Chapter 10 16-Bit Inverter Timer/Counter R; Features - NEC V850E/PH2 User Manual

10.1 Features

Timer R is a 16-bit timer/counter that provides various motor control functions.
• Count clock resolution: 31.25 ns min. (when using 32 MHz count clock)
• General-purpose timer and operation mode supporting various motor control methods
• Compare registers with reload buffers
• 10-bit dead time counter
- Dead time value independently settable through normal phase → inverted phase → normal
phase
• A/D conversion trigger signal generation
- Generation of A/D conversion trigger with 2 compare registers, TRnCCR4 and TRnCCR5
- Dedicated output pin (TORn7) set with the TRnADTRG0 signal and reset with the TRnADTRG1
signal
• Interrupt thinning out function
- Thinning out rates of 1/1 to 1/32
• Forced output stop function: ESO
- High-impedance output of pins TORn0 to TORn7 possible during ESOn input
• Compare value setting
- Reload (batch rewrite)/anytime rewrite mode selectable
• Reload mode
- Reload enabled by writing to TRnCCR1 register last, multiple registers simultaneity maintained
- Peak/valley/peak and valley reload, transfer possible at reload timing
- Provision of reload request flag TRnRSF
- DMA transferable register address placement
• High-accuracy T-PWM mode
- 0 to 100% duty PWM output possible, including dead time reduction
- Increased output resolution without software load, because presence/absence of added pulse to
PWM output on up-count side can be controlled with LSB of compare register
8 selectable count clocks: φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/256, φ/1024
•
• Active level of output pins TORn0 to TORn7 settable for each pin
• Fail-safe function (error interrupt output possible)
- Simultaneous active output detection function in normal phase/inverted phase
Note: High-accuracy T-PWM mode

Chapter 10 16-bit Inverter Timer/Counter R

User's Manual U16580EE3V1UD00
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