Figure 2-2: Noise Removal Time Control Register (1/2) - NEC V850E/PH2 User Manual

(1) Noise removal time control register (NRC)
The NRC register specifies the noise removal clock setting for different edge sensitive inputs.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
NRC NCR7
NCR7
0
1
NCR6
0
1
NCR5
0
1
NCR4
0
1
NCR3
0
1
NCR2
0
1
Note: Input pins TIC00, TIC01, TCRL0, TCUD0, and TIUD0 are not available on μPD70F3447
82
Chapter 2 Pin Functions

Figure 2-2: Noise Removal Time Control Register (1/2)

R/W
6 5
NCR6 NCR5
Noise removal clock setting for input pins TIR10 to TIR13, TEVTR1, TTRGR1
f /16
XX
f /64
XX
Noise removal clock setting for input pins TIP60, TIP61, TIP70, TIP71,
TEVTP6, TEVTP7, TTRGP6, TTRGP7
f /16
XX
f /64
XX
Noise removal clock setting for input pins TIP40, TIP41, TIP50, TIP51,
TEVTP4, TEVTP5, TTRGP4, TTRGP5
f /16
XX
f /64
XX
Noise removal clock setting for input pins TIP20, TIP21, TIP30, TIP31,
TEVTP2, TEVTP3, TTRGP2, TTRGP3
f /16
XX
f /64
XX
Noise removal clock setting for input pins TIP00, TIP01, TIP10, TIP11,
TEVTP0, TEVTP1, TTRGP0, TTRGP1
f /16
XX
f /64
XX
Noise removal clock setting for input pins INTP12, TICC00, TICC01, TCLR0,
TCUD0, TIUD0, TIT00, TIT01, TIT10, TIT11, TECRT0, TECRT1, TEVTT0,
TEVTT1, TTRGT0, TTRGT1, TENCT00, TENCT01, TENCT10, TENCT11
f /16
XX
f /64
XX
User's Manual U16580EE3V1UD00
Address: FFFFF7A0H
4 3
NCR4 NCR3
2 1
NCR2 NCR1 NCR0
0
Note