Figure 9-9: Tmpn I/O Control Register 2 (Tpnioc2) - NEC V850E/PH2 User Manual

(5) TMPn I/O control register 2 (TPnIOC2)
The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count
input signal (TEVTPn) and external trigger input signal (TTRGPn).
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
TPnIOC2 0
(n = 0 to 7)
TP1EES1 TP1EES0
0
0
1
1
TP1ETS1 TP1ETS0
0
0
1
1
Cautions: 1. Rewrite the TPnEES1, TPnEES0, TPnEST1, and TPnEST0 bits only when TPnCE =
0. (The same value can be written when TPnCE = 1.) If rewriting was mistakenly
performed, set TPnCE = 0 and then set the bits again.
2. The TPnEES1 and TPnEES0 bits are valid only when TPnEEE = 1 or when the
external event count mode (TPnMD2 to TPnMD0 = 001B of the TPnCTL1 register)
has been set.
Remark: n = 0 to 7
Chapter 9 16-Bit Timer/Event Counter P

Figure 9-9: TMPn I/O Control Register 2 (TPnIOC2)

R/W Address:
6 5
0 0
External Event Counter Input (TEVTPn) Valid Edge Setting
0 No edge detection (capture operation invalid)
1 Rising edge detection
0 Falling edge detection
1 Both, rising and falling edge detection
External Trigger Input (TTRGPn) Valid Edge Setting
0 No edge detection (capture operation invalid)
1 Rising edge detection
0 Falling edge detection
1 Both, rising and falling edge detection
User's Manual U16580EE3V1UD00
TP0IOC2 FFFFF604H, TP1IOC2 FFFFF614H,
TP2IOC2 FFFFF624H, TP3IOC2 FFFFF634H,
TP4IOC2 FFFFF644H, TP5IOC2 FFFFF654H,
TP6IOC2 FFFFF664H, TP7IOC2 FFFFF674H,
TP8IOC2 FFFFF684H
4 3 2
0 TPnEES1 TPnEES0 TPnETS1 TPnETS0
1 0
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