Interrupt Mask Registers 0 To 2 (Imr0 To Imr2) - NEC V850ES/SA2 UPD703201 Manual

14.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2)

These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR2
registers is equivalent to the xxMKn bit of the xxICn register.
The IMRm register can be read or written in 16-bit units (m = 0 to 2).
If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register,
these registers can be read or written in 8-bit or 1-bit units (m = 0 to 2).
Bits 15 to 6 of the IMR2 register (bits 7 to 0 of the IMR2H register and bits 7 and 6 of the IMR2L register) are fixed
to 1. If these bits are not 1, the operation cannot be guaranteed.
Caution The device file defines the xxMKn bit of the xxICn register as a reserved word. If a bit is
manipulated using the name of xxMKn, the contents of the xxICn register, instead of the IMRm
register, are rewritten (as a result, the contents of the IMRm register are also rewritten).
After reset:
IMR2
After reset:
IMR1 ADMK
SRMK0
After reset:
IMR0 TMMK2
PMK6
xxMKn
Note This bit is valid only for the V850ES/SA3. In the V850EA/SA2, be sure to set this bit to 1.
Remark xx: Identification name of each peripheral unit (AD, BRG, CC, CSI, DMA, IIC, OVF, D, ROV, RTC,
SRE, ST, TM, WDT).
n: Peripheral unit number (None, or 0 to 3)
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CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
FFFFH R/W Address:
15 14 13
1 1 1
7 6 5
1 1 BRGMK
FFFFH R/W Address:
15 14 13
Note
CSIMK4 CSIMK3
7 6 5
SREMK0 CSIMK1
FFFFH R/W Address:
15 14 13
OVFMK1 CCMK11 CCMK10
7 6 5
PMK5 PMK4
Interrupt mask flag setting
0 Interrupt servicing enabled
1
Interrupt servicing disabled
Preliminary User's Manual U15905EJ1V0UD
FFFFF104H
12 11 10
1 1 1
4 3 2
OVFMK DMAMK3 DMAMK2
FFFFF102H
12 10
11
STMK1 SRMK1 SREMK1
4 3 2
IICMK CSIMK0 TMMK5
FFFFF100H
12 10
11
OVFMK0 CCMK01
4 3 2
PMK3 PMK2 PMK1
9 8
1 1
1 0
DMAMK1 DMAMK0
9
8
CSIMK2 STMK0
1 0
TMMK4 TMMK3
9
8
CCMK00 RTCMK
1 0
PMK0 WDTMK