NEC V850E/PH2 User Manual page 790

(11) CnINTS - CANn module interrupt status register
The CnINTS register indicates the interrupt status of the CAN module.
After reset: 0000H R/W
(a) Read
15
CnINTS 0
7
0
CINTS5 to CINTS0
0
1
Interrupt status bit
CINTS5
CINTS4
CINTS3
CINTS2
CINTS1
CINTS0
Note: The CINTS5 bit is set only when the CAN module is woken up from the CAN sleep mode by a
CAN bus operation. The CINTS5 bit is not set when the CAN sleep mode has been released by
software.
(b) Write
15
CnINTS 0
7
0
Clear
CINTS5 to CINTS0
0
1
Caution: Please clear the status bit of this register with software when the confirmation of
each status is necessary in the interrupt processing, because these bits are not
cleared automatically.
790
Chapter 18 AFCAN Controller
Address: CnINTS <CnRBaseAddr> + 058
14 13
0 0
6 5
0 CINTS5
No related interrupt source event is pending.
A related interrupt source event is pending.
Wakeup interrupt from CAN sleep mode
Arbitration loss interrupt
CAN protocol error interrupt
CAN error status interrupt
Interrupt on completion of reception of valid message frame to message buffer m
Interrupt on normal completion of transmission of message frame from message
buffer m
14 13
0 0
6 5
Clear
0
CINTS5
CINTS5 to CINTS0 bits are not changed.
CINTS5 to CINTS0 bits are cleared to 0.
User's Manual U16580EE3V1UD00
H
12 11
0 0
4 3
CINTS4 CINTS3 CINTS2
CAN interrupt status bit
Related interrupt source event
Note
12 11
0 0
4 3
Clear Clear
CINTS4 CINTS3 CINTS2
Setting of CINTS5 to CINTS0 bits
10 9
0 0
2 1
CINTS1 CINTS0
10 9
0 0
2 1
Clear Clear Clear
CINTS1 CINTS0
8
0
0
8
0
0