System Clock Output Disabling Function - Hitachi H8/3008 Hardware Manual

18.7

System Clock Output Disabling Function

Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the
PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high-
impedance state. Figure 18.3 shows the timing of the stopping and starting of system clock output.
When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 18.4 indicates
the state of the φ pin in various operating states.
MSTCRH write cycle
T1
φ pin
Figure 18.3 Starting and Stopping of System Clock Output
Table 18.4 φ Pin State in Various Operating States
Operating State
Hardware standby
Software standby
Sleep mode
Normal operation
450
(PSTOP = 1)
T2 T3
PSTOP = 0
High impedance
Always high
System clock output
System clock output
High impedance
MSTCRH write cycle
(PSTOP = 0)
T1 T2 T3
PSTOP = 1
High impedance
High impedance
High impedance
High impedance