Table 2-7 Clock Division Ratio; Table 2-8 Input Clock Of Baud Rate Generator - Fujitsu F2MC-8L Family series Hardware Manual

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Peripherals
CS1
0
0
1
1
HARDWARE CONFIGURATION
As shown in the figure, data transfer starts from the start bit (Low-level data),
the data bit length specified by the LSB first is transferred, and transfer ends
at the stop bit (High-level data).
In asynchronous transfer, the relationship between SCK and SI is not as
shown in the above figure. In addition, at asynchronous transfer, the
relationship is not as shown in the above diagram even when SCK is set to
input.
(d) Transfer clock selection
The transfer clock can be selected from the external clock (SCK pin), PWM
timer, and the dedicated baud rate generator. This selection is done by the
CS0, CS1, and CR bits of the serial rate control register (SRC). The division
ratios are listed in Table 2–7.
Table 2–7 Clock Division Ratio
CS0
Clock Input
0
External clock
1
PWM timer
0
Dedicated baud
rate generator
1
When using the dedicated baud rate generator, select the input clock of the
baud rate generator by PDS1 and PDS0 of the SMC2. indicates the input
clocks to be used and the division, and Table 2–9 indicates the reference
baud rates.
Table 2–8 Input Clock of Baud Rate Generator
PDS1
PDS0
0
0
0
1
1
0
1
1
2– 48
CR
Asynchronous
0
1/16
1
1/64
0
1/16
1
1/64
0
1/16
1
1/64
---
1/8
Division
Clock
1/4
CPU operation
1/6
CPU operation
1/13
CPU operation
1/65
CPU operation
Sychronous
1/1
1/2
1/2
1/1

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