Debug Mcu Configuration Register - ST STM32F413 Reference Manual

Debug support (DBG)
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
•
In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by
the debugger. This will feed HCLK with the same clock that is provided to FCLK
(system clock previously configured by the software).
•
In Stop mode, the bit DBG_STOP must be previously set by the debugger. This will
enable the internal RC oscillator clock to feed FCLK and HCLK in STOP mode.
34.16.2 Debug support for timers, watchdog, bxCAN and I
During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
•
They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
•
They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the bxCAN, the user can choose to block the update of the receive register during a
breakpoint.
2
For the I
34.16.3

Debug MCU configuration register

This register allows the configuration of the MCU under DEBUG. This concerns:
•
Low-power mode support
•
Timer and watchdog counter support
•
Trace pin assignment
This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
DBGMCU_CR register
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
1266/1284
C, the user can choose to block the SMBUS timeout during a breakpoint.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
DocID029473 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
TRACE_
TRACE
Res. MODE
_IOEN
[1:0]
rw rw rw
2
C
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
DBG_
DBG_
Res. Res. STAND
STOP
BY
rw rw
RM0430
16
Res.
0
DBG_
SLEEP
rw