Device Programming Model - ST STM32F413 Reference Manual

RM0430
•
Selecting the queue depth
Choose the periodic and non-periodic request queue depths carefully to match the
number of periodic/non-periodic endpoints accessed.
The non-periodic request queue depth affects the performance of non-periodic
transfers. The deeper the queue (along with sufficient FIFO size), the more often the
core is able to pipeline non-periodic transfers. If the queue size is small, the core is
able to put in new requests only when the queue space is freed up.
The core's periodic request queue depth is critical to perform periodic transfers as
scheduled. Select the periodic queue depth, based on the number of periodic transfers
scheduled in a microframe. If the periodic request queue depth is smaller than the
periodic transfers scheduled in a microframe, a frame overrun condition occurs.
• Handling babble conditions
OTG_FS controller handles two cases of babble: packet babble and port babble.
Packet babble occurs if the device sends more data than the maximum packet size for
the channel. Port babble occurs if the core continues to receive data from the device at
EOF2 (the end of frame 2, which is very close to SOF).
When OTG_FS controller detects a packet babble, it stops writing data into the Rx
buffer and waits for the end of packet (EOP). When it detects an EOP, it flushes already
written data in the Rx buffer and generates a Babble interrupt to the application.
When OTG_FS controller detects a port babble, it flushes the Rx FIFO and disables the
port. The core then generates a Port disabled interrupt (HPRTINT in OTG_GINTSTS,
PENCHNG in OTG_HPRT). On receiving this interrupt, the application must determine
that this is not due to an overcurrent condition (another cause of the Port Disabled
interrupt) by checking POCA in OTG_HPRT, then perform a soft reset. The core does
not send any more tokens after it has detected a port babble condition.
Note: The content of this section applies only to USB OTG HS.
33.16.5

Device programming model

Endpoint initialization on USB reset
1. Set the NAK bit for all OUT endpoints
–
2. Unmask the following interrupt bits
–
–
–
–
–
–
3. Set up the Data FIFO RAM for each of the FIFOs
–
SNAK = 1 in OTG_DOEPCTLx (for all OUT endpoints)
INEP0 = 1 in OTG_DAINTMSK (control 0 IN endpoint)
OUTEP0 = 1 in OTG_DAINTMSK (control 0 OUT endpoint)
STUPM = 1 in OTG_DOEPMSK
XFRCM = 1 in OTG_DOEPMSK
XFRCM = 1 in OTG_DIEPMSK
TOM = 1 in OTG_DIEPMSK
Program the OTG_GRXFSIZ register, to be able to receive control OUT data and
setup data. If thresholding is not enabled, at a minimum, this must be equal to 1
DocID029473 Rev 3
USB on-the-go full-speed (OTG_FS)
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