ST STM32F413 Reference Manual page 1180

USB on-the-go full-speed (OTG_FS)
Bit 15 USBAEP: USB active endpoint
Bits 14:11 Reserved, must be kept at reset value.
Bits 10:0 MPSIZ: Maximum packet size
33.15.44 OTG device endpoint-x interrupt register (OTG_DIEPINTx)
(x = 0..5, where x = Endpoint_number)
Address offset: 0x908 + (Endpoint_number × 0x20)
Reset value: 0x0000 0080
This register indicates the status of an endpoint with respect to USB- and AHB-related
events. It is shown in
endpoints interrupt bit of the Core interrupt register (IEPINT in OTG_GINTSTS) is set.
Before the application can read this register, it must first read the device all endpoints
interrupt (OTG_DAINT) register to get the exact endpoint number for the Device endpoint-x
interrupt register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 TXFE: Transmit FIFO empty
Bit 6 INEPNE: IN endpoint NAK effective
Bit 5 Reserved, must be kept at reset value.
1180/1284
Indicates whether this endpoint is active in the current configuration and interface. The core
clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving
the SetConfiguration and SetInterface commands, the application must program endpoint
registers accordingly and set this bit.
The application must program this field with the maximum packet size for the current logical
endpoint. This value is in bytes.
Figure 388. The application must read this register when the IN
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely
empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in
the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG).
This bit can be cleared when the application clears the IN endpoint NAK by writing to the
CNAK bit in OTG_DIEPCTLx.
This interrupt indicates that the core has sampled the NAK bit set (either by the application
or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application
has taken effect in the core.
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit
takes priority over a NAK bit.
24 23 22
Res. Res. Res.
8 7 6
INEP
Res. TXFE
NE
r r
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21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. ITTXFE TOC Res.
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RM0430
17 16
Res. Res.
1 0
EP
XFRC
DISD
rc_w1 rc_w1