Otg_Fs Register Map - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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Bit 5 ENL1GTG: Enable Sleep clock gating

Bit 4 PHYSUSP: PHY Suspended

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 GATEHCLK: Gate HCLK

Bit 0 STPPCLK: Stop PHY clock

33.15.52 OTG_FS register map

The table below gives the USB OTG register map and reset values.

When this bit is set, core internal clock gating is enabled in Sleep state if the core cannot

assert utmi_l1_suspend_n. When this bit is not set, the PHY clock is not gated in Sleep

Indicates that the PHY has been Suspended. This bit is updated once the PHY is

Suspended after the application has set the STPPCLK bit.

The application sets this bit to gate HCLK to modules other than the AHB Slave and Master

and wakeup logic when the USB is suspended or the session is not valid. The application

clears this bit when the USB is resumed or a new session starts.

The application sets this bit to stop the PHY clock when the USB is suspended, the session

is not valid, or the device is disconnected. The application clears this bit when the USB is

resumed or a new session starts.

Table 212. OTG_FS register map and reset values

DocID029473 Rev 3

USB on-the-go full-speed (OTG_FS)