Id Codes And Locking Mechanism - ST STM32F413 Reference Manual

RM0430
34.6

ID codes and locking mechanism

There are several ID codes inside the MCUs. ST strongly recommends tools designers to
lock their debuggers using the MCU DEVICE ID code located in the external PPB memory
map at address 0xE0042000.
34.6.1 MCU device ID code
The MCUs integrate an MCU ID code. This ID identifies the ST MCU part-number and the
die revision. It is part of the DBG_MCU component and is mapped on the external PPB bus
(see Section 34.16 on page
5 pins) or the SW debug port (two pins) or by the user software. It is even accessible while
the MCU is under system reset.
Only the DEV_ID(11:0) should be used for identification by the debugger/programmer tools.
DBGMCU_IDCODE
Address: 0xE004 2000
Only 32-bits access supported. Read-only.
31 30 29 28
r r r
15 14 13 12
Res. Res. Res. Res.
Bits 31:16 REV_ID(15:0) Revision identifier
Bits 15:12
Bits 11:0 DEV_ID(11:0): Device identifier
34.6.2 Boundary scan TAP
JTAG ID code
The TAP of the BSC (boundary scan) integrates a JTAG ID code equal to: 0x0645 8041
34.6.3 Cortex
The TAP of the ARM
®
ARM default one and has not been modified. This code is only accessible by the JTAG
Debug Port.
This code is 0x4BA0 0477 (corresponds to Cortex
Reference ARM®
1265). This code is accessible using the JTAG debug port (4 to
27 26 25
r r r r
11 10 9
r r r
This field indicates the revision of the device:
0x1000 = Revision A
Reserved, must be kept at reset value.
The device ID is 0x463
®
-M4 with FPU TAP
® ®
Cortex
documentation).
24 23 22
REV_ID
r r r
8 7 6
DEV_ID
r r r
-M4 with FPU integrates a JTAG ID code. This ID code is the
®
-M4 with FPU r0p1, see
DocID029473 Rev 3
Debug support (DBG)
21 20 19 18
r r r r
5 4 3 2
r r r r
17 16
r r
1 0
r r
Section 34.2:
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