Pci Error Handling - Intel S3000PT - Server Board Motherboard Specification

Functional Architecture Intel® Server Board S3000PT TPS
3.4.2.4 Serialized IRQ Support
The Intel® Server Board S3000PT supports a serialized interrupt delivery mechanism.
Serialized Interrupt Requests (SERIRQ) consists of a start frame, a minimum o f 17 IRQ / data
channels, and a stop frame. Any slave device in the quiet mode may initiate the start frame.
While in the continuous mode, the start frame is initiated by the host controller.
3.5

PCI Error Handling

The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry
the offending transaction, or to report it using SERR#. All other PCI -related errors are reported
by SERR#. SERR# is routed to the NMI if enabled by the BIOS.
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