Register 8: Tlb Operations - Intel PXA255 User Manual

Configuration
Table 7-12. Cache Functions (Sheet 2 of 2)
Drain Write (& Fill) Buffer
Invalidate Branch Target Buffer
Allocate Line in the Data Cache
The line-allocate command allocates a tag into the data cache specified by bits [31:5] of Rd. If a
valid dirty line (with a different MVA) already exists at this location it will be evicted. The 32 bytes
of data associated with the newly allocated line are not initialized and therefore will generate
unpredictable results if read.
This command may be used for cleaning the entire data cache on a context switch and also when
re-configuring portions of the data cache as data RAM. In both cases, Rd is a virtual address that
maps to some non-existent physical memory. When creating data RAM, software must initialize
the data RAM before read accesses can occur. Specific uses of these commands can be found in
Chapter 6, "Data
Other items to note about the line-allocate command are:
•
It forces all pending memory operations to complete.
•
If the targeted cache line is already resident, this command has no effect.
•
This command cannot be used to allocate a line in the mini Data Cache.
•
The newly allocated line is not marked as "dirty". However, if a valid store is made to that line
it will be marked as "dirty" and will get written back to external memory if another line is
allocated to the same cache location. This eviction will produce unpredictable results if the
line-allocate command used a virtual address that mapped to non-existent memory.
To avoid this situation, the line-allocate operation should only be used if one of the following
can be guaranteed:
— The virtual address associated with this command is not one that will be generated during
normal program execution. This is the case when line-allocate is used to clean/invalidate
the entire cache.
— The line-allocate operation is used only on a cache region destined to be locked. When the
region is unlocked, it must be invalidated before making another data access.
7.2.8

Register 8: TLB Operations

Disabling/enabling the MMU has no effect on the contents of either TLB: valid entries stay valid,
locked items remain locked. To invalidate the TLBs the commands below are required. All
operations defined in
This register is write-only. Reads from this register, as with an MRC, have an undefined effect.
7-10
Function opcode_2
0b100
0b110
0b101
Cache".
Table 7-13 work regardless of whether the cache is enabled or disabled.
CRm Data
0b1010 Ignored
0b0101 Ignored
0b0010 MVA
Intel® XScale™ Microarchitecture User's Manual
Instruction
MCR p15, 0, Rd, c7, c10, 4
MCR p15, 0, Rd, c7, c5, 6
MCR p15, 0, Rd, c7, c2, 5