Cp15 Registers - Intel PXA255 User Manual

Xscale microarchitecture
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Table 7-2. LDC/STC Format when Accessing CP14 (Sheet 2 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Bits
20
19:16
15:12
11:8
7:0
7.2

CP15 Registers

Table 7-3
Table 7-3. CP15 Registers
Register (CRn)
0
0
1
1
2
3
4
5
6
7
8
9
10
11 - 12
13
14
15
Intel® XScale™ Microarchitecture User's Manual
1 1 0 P U N W L
Description
L - Load or Store
0 = STC
1 = LDC
Rn - specifies the base register
CRd - specifies the coprocessor register
cp_num - coprocessor number
8-bit word offset
lists the CP15 registers implemented in the Intel® XScale™ core.
Opcode_2
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Rn
CRd
-
-
-
The Intel® XScale™ core defines the
following:
0b1110 = CP14
CP0-13 & CP15 = Undefined Exception
-
Access
Read / Write-Ignored
Read / Write-Ignored
Read / Write
Read / Write
Read / Write
Read / Write
Unpredictable
Read / Write
Read / Write
Read-unpredictable / Write
Read-unpredictable / Write
Read / Write
Read / Write
Unpredictable
Read / Write
Read / Write
Read / Write
Configuration
8
7
6
5
4
3
cp_num
8_bit_word_offset
Notes
Description
ID
Cache Type
Control
Auxiliary Control
Translation Table Base
Domain Access Control
Reserved
Fault Status
Fault Address
Cache Operations
TLB Operations
Cache Lock Down
TLB Lock Down
Reserved
Process ID (PID)
Breakpoint Registers
(CRm = 1) CP Access
2
1
0
7-3

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