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Software Debug
Another possibility is for a more complete debug handler to be downloaded during reset. The
debug handler may support some operations, such as read memory, write memory, etc. However,
other operations, such as reading or writing a group of CP registers, can be downloaded
dynamically. This method could be used to dynamically download infrequently used debug handler
functions, while the more common operations remain static in the mini-instruction cache.
10.13.6
Mini Instruction Cache Overview
The mini instruction cache is a smaller version of the main instruction cache (Refer to Chapter 4
for more details on the main instruction cache). It is a 2KB, 2-way set associative cache. There are
32 sets, each containing two ways; each way contains 8 words. The cache uses the round-robin
replacement policy for lines overloaded from the debugger.
Normal application code is never cached in the mini instruction cache on an instruction fetch. The
only way to get code into the mini instruction cache is through the JTAG LDIC function. Code
downloaded into the mini instruction cache is essentially locked - it cannot be overwritten by
application code running on the Intel® XScale™ core. It is not locked against code downloaded
through the JTAG LDIC functions.
Application code can invalidate a line in the mini instruction cache using a CP15 Invalidate IC line
function to an address that hits in the mini instruction cache. However, a CP15 global invalidate IC
function does not affect the mini instruction cache.
The mini instruction cache can be globally invalidated through JTAG by the LDIC Invalidate IC
function or by a processor reset when the processor is not in HALT or LDIC mode. A single line in
the mini instruction cache can be invalidated through JTAG by the LDIC Invalidate IC-line
function.
The mini instruction cache is virtually addressed and addresses may be remapped by the PID.
However, since the debug handler executes in Special Debug State, address translation and PID
remapping are turned off. For application code, accesses to the mini instruction cache use the
normal address translation and PID mechanisms.
10.14
Halt Mode Software Protocol
This section describes the overall debug process in Halt Mode. It describes how to start and end a
debug session and provides details for implementing a debug handler. Intel may provide a standard
Debug Handler that implements some of the techniques in this chapter. This code and other
documentation describing additional handler implementation techniques and requirements is
intended for manufacturers of debugging tools.
10.14.1
Starting a Debug Session
Prior to starting a debug session in Halt Mode, the debugger must download code into the
instruction cache during reset, via JTAG.
Cache"). This downloaded code should consist of:
•
a debug handler;
•
an override default vector table;
•
an override relocated vector table (if necessary).
10-40
(Section 10, "Downloading Code into the Instruction
Intel® XScale™ Microarchitecture User's Manual
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