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Table 3-2. Data Cache and Buffer Behavior when X = 1
C B
Cacheable?
0 0
0 1
1 0
1 1
a.
Normally, bufferable writes can coalesce with previously buffered data in the same address range
b.
See
Section 7.2.2
3.2.4
Details on Data Cache and Write Buffer Behavior
If the MMU is disabled all data accesses will be non-cacheable and non-bufferable. This is the
same behavior as when the MMU is enabled, and a data access uses a descriptor with X, C, and B
all set to 0.
The X, C, and B bits determine when the processor should place new data into the Data Cache. The
cache places data into the cache in lines (also called blocks). Thus, the basis for making a decision
about placing new data into the cache is a called a "Line Allocation Policy".
If the Line Allocation Policy is read-allocate, all load operations that miss the cache request a 32-
byte cache line from external memory and allocate it into either the data cache or mini-data cache
(this is assuming the cache is enabled). Store operations that miss the cache will not cause a line to
be allocated.
If read/write-allocate is in effect, load or store operations that miss the cache will request a 32-byte
cache line from external memory if the cache is enabled.
The other policy determined by the X, C, and B bits is the Write Policy. A write-through policy
instructs the Data Cache to keep external memory coherent by performing stores to both external
memory and the cache. A write-back policy only updates external memory when a line in the cache
is cleaned or needs to be replaced with a new line. Generally, write-back provides higher
performance because it generates less data traffic to external memory.
More details on cache policies can be found in
3.2.5
Memory Operation Ordering
A fence memory operation (memop) is one that guarantees all memops issued prior to the fence
will execute before any memop issued after the fence. Thus software may issue a fence to impose a
partial ordering on memory accesses.
Table 3-3 on page 3-4
Intel® XScale™ Microarchitecture User's Manual
Bufferable?
-
-
N
Y
(Mini Data
-
Cache)
Y
Y
for a description of this register
shows the circumstances in which memops act as fences.
Line
Write Policy
Allocation
Policy
-
-
-
-
-
-
Read/Write
Write Back
Allocate
Section 6.2.3, "Cache Policies" on page
Memory Management
Notes
Unpredictable -- do not use
Writes will not coalesce into
a
buffers
Cache policy is determined
by MD field of Auxiliary
b
Control register
6-4.
3-3
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