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Software Debug
The following debug exceptions cause pre-fetch aborts:
•
instruction breakpoint
•
BKPT instruction
The processor ignores vector traps during monitor mode.
When an exception occurs in monitor mode, the processor takes the following actions:
1. disables the trace buffer
2. sets DCSR.moe encoding
3. sets FSR[9]
4. R14_abt = PC of the next instruction to execute + 4 (for Data Aborts)
R14_abt = PC of the faulting instruction + 4 (for Prefetch Aborts)
5. SPSR_abt = CPSR
6. CPSR[4:0] = 0b10111 (ABORT mode)
7. CPSR[5] = 0
8. CPSR[6] = unchanged
9. CPSR[7] = 1
10. PC = 0xc (for Prefetch Aborts),
PC = 0x10 (for Data Aborts)
During Abort mode, external Debug breaks and trace buffer full breaks are internally postponed.
When the processor exits Abort mode, either through a CPSR restore or a write directly to the
CPSR, the postponed Debug breaks will immediately generate a Debug exception. Any of these
postponed Debug breaks are cleared once any one Debug exception occurs.
When exiting, the debug handler should do a CPSR restore operation that branches to the next
instruction to be executed in the program under debug.
10.5
HW Breakpoint Resources
The Intel® XScale™ core debug architecture defines two instruction and two data breakpoint
registers, denoted IBCR0, IBCR1, DBR0, and DBR1.
The instruction and data address breakpoint registers are 32-bit registers. The instruction
breakpoint causes a break before execution of the target instruction. The data breakpoint causes a
break after the memory access has been issued.
In this section Modified Virtual Address (MVA) refers to the virtual address ORed with the PID.
Refer to
Section 7.2.11, "Register 13: Process ID" on page 7-12
processor does not OR the PID with the specified breakpoint address prior to doing address
comparison. This must be done by the programmer and written to the breakpoint register as the
MVA. This applies to data and instruction breakpoints.
10-8
for more details on the PID. The
Intel® XScale™ Microarchitecture User's Manual
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