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Software can lock down several different routines located at different memory locations. This may
cause some sets to have more locked lines than others as shown in
Example 4-4, Locking Code into the Instruction Cache
this example, might be locked into the instruction cache. This example is incomplete as it doesn't
take into account the notes on
locking code is placed by the assembler above the code to be locked in memory to avoid the
prefetch issue, then the notes can be satisfied.
Example 4-4. Locking Code into the Instruction Cache
lockMe:
. . .
lockMeEnd:
codeLock:
lockLoop:
4.3.5
Unlocking Instructions in the Instruction Cache
The Intel® XScale™ core provides a global unlock command for the instruction cache. There is no
unlock function for individual lines in the cache.
Writing to coprocessor 15, register 9 unlocks all the locked lines in the instruction cache and leaves
them valid. These lines then become available for the round-robin replacement algorithm. (See
Table 7-14, "Cache Lockdown Functions" on page 7-11
Intel® XScale™ Microarchitecture User's Manual
page
; This is the code that will be locked into the cache
mov r0, #5
add r5, r1, r2
. . .
; here is the code to lock the "lockMe" routine
ldr r0, =(lockMe AND NOT 31); r0 gets a pointer to the 1st line locked
ldr r1, =(lockMeEnd AND NOT 31); r1 contains a pointer to the last line
mcr p15, 0, r0, c9, c1, 0; lock next line of code into I-Cache
cmp r0, r1
; are we done yet?
add r0, r0, #32
; advance pointer to next line
bne lockLoop
; if not done, do the next line
shows how a routine, called "lockMe" in
4-6. However if this code runs with interrupts disabled and the
for the exact command.)
Instruction Cache
Figure
4-2.
4-7
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