Sleep Mode Timing; Sleep Mode Timing Specifications - Intel PXA255 Datasheet

Electrical Specifications
Figure 6. Sleep Mode Timing
nVDD_FAULT
nRESET_OUT
Table 18. Sleep Mode Timing Specifications
Symbol
tA_GP[x}
tD_PWR_F
tD_PWR_R
tDSM_VCC
tD_FAULT
tDSM_OUT
tDSM_OUT_F
tDSM_OUT_O
t
DSM_NCS0
NOTE: For the parameter t
VCC regulator must be stable within the stated maximum for the processor to function correctly.
Factors such as external voltage regulator ramp time and bulk capacitance will affect the ramp time of
the internal regulator and must be taken into account when designing the system.
34
GP[x]
PWR_EN
VCC
Note: nBA TT_FAULT must be high or Cotulla will not exit Sleep Mode
Note: nBATT_FAULT must be high or the PXA255 processor
will not exit sleep mode.
Description
Assert time of GPIO wake-up source
(x=[15:0])
Delay from nRESET_OUT asserted to
PWR_EN de-asserted
Delay between GP[x] asserted to
PWR_EN asserted
Delay between PWR_EN asserted and
VCC stable
Delay between PWR_EN asserted and
nVDD_FAULT de-asserted
Delay between PWR_EN asserted and
nRESET_OUT de-asserted, OPDE set
Delay between PWR_EN asserted and
nRESET_OUT de-asserted, FWAKE set
Delay between PWR_EN asserted and
nRESET_OUT de-asserted, OPDE
clear
Delay between nReset_Out de-asserted
and nCS0 asserted
, VCC refers to the VCC supply internal to the processor. The internal
DSM_VCC
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
t
A_GP[x]
t
t
D_PWR_R
D_PWR_F
Min Typical
91.6
61
30.5
28.0
—
10.35
180.84
t
DSM_VCC
t
D_F A UL T
t
DSM_OUT
Max Units
— — µs
µs
— 91.6
— 122.1 µs
— 10 ms
— 10 ms
— 28.5 ms
— 650 µs
— 10.5 ms
— 332 ns