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10.5.1
Instruction Breakpoints
The Debug architecture defines two instruction breakpoint registers (IBCR0 and IBCR1). The
format of these registers is shown in Table 10-5., Instruction Breakpoint Address and Control
Register (IBCRx). In ARM* mode, the upper 30 bits contain a word aligned MVA to break on. In
Thumb mode, the upper 31 bits contain a half-word aligned MVA to break on. In both modes, bit 0
enables and disables that instruction breakpoint register. Enabling instruction breakpoints while
debug is globally disabled (DCSR.GE=0) will result in unpredictable behavior.
Table 10-5. Instruction Breakpoint Address and Control Register (IBCRx)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable address, disabled
Bits
31:1
0
An instruction breakpoint will generate a debug exception before the instruction at the address
specified in the IBCR executes. When an instruction breakpoint occurs, the processor sets the
DBCR[MOE] bits to 0b001.
Software must disable the breakpoint before exiting the handler. This allows the breakpointed
instruction to execute after the exception is handled.
Single step execution is accomplished using the instruction breakpoint registers and must be
completely handled in software (either on the host or by the debug handler).
10.5.2
Data Breakpoints
The Intel® XScale™ core debug architecture defines two data breakpoint registers (DBR0,
DBR1). The format of the registers is shown in
Table 10-6. Data Breakpoint Register (DBRx)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
DBR0 is a dedicated data address breakpoint register. DBR1 can be programmed for 1 of 2
operations:
Intel® XScale™ Microarchitecture User's Manual
Access
Read / Write
Read / Write
Access
Read / Write
IBCRx
Description
Instruction Breakpoint MVA
in ARM* mode, IBCRx[1] is ignored
IBCRx Enable (E) -
0 = Breakpoint disabled
1 = Breakpoint enabled
Table
10-6.
DBRx
Description
DBR0: Data Breakpoint MVA
DBR1:
Data Address Mask OR
Data Breakpoint MVA
Software Debug
8
7
6
5
4
3
2
1
0
E
8
7
6
5
4
3
2
1
0
10-9
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