Table of Contents
Advertisement
Programming Model
2.2.3
ARM* DSP-Enhanced Instruction Set
The Intel® XScale™ core implements ARM*'s DSP-enhanced instruction set. There are new
multiply instructions that operate on 16-bit data values and new saturation instructions. Some of
the new instructions are:
•
SMLAxy32<=16x16+32
•
SMLAWy 32<=32x16+32
•
SMLALxy64<=16x16+64
•
SMULxy32<=16x16
•
SMULWy32<=32x16
•
QADDadds two registers and saturates the result if an overflow occurred
•
QDADDdoubles and saturates one of the input registers then add and saturate
•
QSUBsubtracts two registers and saturates the result if an overflow occurred
•
QDSUBdoubles and saturates one of the input registers then subtract and saturate
The Intel® XScale™ core also implements LDRD, STRD and PLD instructions with the following
implementation notes:
•
PLD is interpreted as a read operation by the MMU and is ignored by the data breakpoint unit,
i.e., PLD will never generate data breakpoint events.
•
PLD to a non-cacheable page performs no action. Also, if the targeted cache line is already
resident, this instruction has no effect.
•
Both LDRD and STRD instructions will generate an alignment exception when the address is
not on a 64-bit boundary.
MCRR and MRRC are only supported on the Intel® XScale™ core when directed to coprocessor 0
and are used to access the internal accumulator. See
to other coprocessors on the application processor generates the Undefined instruction exception.
2.2.4
Base Register Update
If a data abort is signalled on a memory instruction that specifies writeback, the contents of the
base register will not be updated. This holds for all load and store instructions. This behavior
matches that of the first generation StrongARM* processor and is referred to in the ARM* V5
architecture as the Base Restored Abort Model.
2.3
Extensions to ARM* Architecture
The Intel® XScale™ core made a few extensions to the ARM* Version 5 architecture to meet the
needs of various markets and design requirements. The following is a list of the extensions which
are discussed in the next sections.
•
A DSP coprocessor (CP0) has been added that contains a 40-bit accumulator and 8 new
operations in coprocessor space, hereafter referred to as new instructions.
2-2
Section 2.3.1.2
for more information. Access
Intel® XScale™ Microarchitecture User's Manual
Advertisement
Table of Contents
