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Configuration
Table 7-6. ARM* Control Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: writable bits set to 0
Bits
31:14
13
12
11
10
9
8
7
6:3
2
1
0
The mini-data cache attribute bits, in the Auxiliary Control Register, are used to control the
allocation policy for the mini-data cache and whether it will use write-back caching or write-
through caching.
The configuration of the mini-data cache must be setup before any data access is made that may be
cached in the mini-data cache. Once data is cached, software must ensure that the mini-data cache
has been cleaned and invalidated before the mini-data cache attributes can be changed.
7-6
Access
Read-Unpredictable /
Write-as-Zero
Read / Write
Read / Write
Read / Write
Read-as-Zero / Write-as-Zero
Read / Write
Read / Write
Read / Write
Read-as-One / Write-as-One
Read / Write
Read / Write
Read / Write
V I
Z 0 R S B 1 1 1 1 C A M
Description
Reserved
Exception Vector Relocation (V).
0 = Base address of exception vectors is 0x0000_0000
1 = Base address of exception vectors is 0xFFFF_0000
Instruction Cache Enable/Disable (I)
0 = Disabled
1 = Enabled
Branch Target Buffer Enable (Z)
0 = Disabled
1 = Enabled
Reserved
ROM Protection (R bit)
This selects the access checks performed by the memory
management unit. See the ARM Architecture Reference
Manual for more information.
System Protection (S bit)
This selects the access checks performed by the memory
management unit. See the ARM Architecture Reference
Manual for more information.
Big/Little Endian (B)
0 = Core Little-endian data operations
1 = Core Big-endian data operation
= 0b1111
Data cache enable/disable (C)
0 = Disabled
1 = Enabled
Alignment fault enable/disable (A)
0 = Disabled
1 = Enabled
Memory management unit enable/disable (M)
0 = Disabled
1 = Enabled
Intel® XScale™ Microarchitecture User's Manual
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