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Software Debug
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HALT mode: active when the Halt Mode bit is set in the DCSR; prevents only the mini
instruction cache from being invalidated; main instruction cache is invalidated by reset.
During a cold reset (in which both a processor reset and a JTAG reset occurs) it can be guaranteed
that the instruction cache will be invalidated since the JTAG reset takes the processor out of any of
the modes listed above.
During a warm reset, if a JTAG reset does not occur, the instruction cache is not invalidated by
reset when any of the above modes are active. This situation requires special attention if code is
downloaded during the warm reset.
Note: While Halt Mode is active, reset can invalidate the main instruction cache. Thus debug handler
code downloaded during reset can only be loaded into the mini instruction cache. However, code
can be dynamically downloaded into the main instruction cache. (refer to
"Dynamically Loading IC After
The following sections describe the steps necessary to ensure code is correctly downloaded into the
instruction cache.
10.13.4.1
Loading IC During Cold Reset for Debug
The
Figure 10-11
cold reset for debug.
NOTE: In the
JTAG IR contains the SELDCSR instruction, the hold_rst signal is set to the value scanned into
DBG_SR[1].
10-34
Reset").
shows the actions necessary to download code into the instruction cache during a
Figure 10-11
hold_rst is a signal that gets set and cleared through JTAG When the
Intel® XScale™ Microarchitecture User's Manual
Section 10,
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