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2. The instruction cache sends a fetch request to the external bus. This request is for a complete
32-byte cache line that will fill in sequence.
3. Instructions words are returned back from the external bus, at a maximum rate of 1 word per
core cycle but typically much slower for Flash or SDRAM. As each word returns, the
corresponding valid bit is set for the word in the currently selected fetch buffer.
4. As soon as the fetch buffer receives the requested instruction, it forwards the instruction to the
instruction decoder for execution. Note at this point, with the pipeline restarting, another
instruction cache miss may occur necessitating the use of the other Instruction Fetch Buffer.
5. When all words to an Instruction Fetch Buffer have returned, the fetched line will be written
into the instruction cache if it's cacheable and if the instruction cache is enabled. The line
chosen for update in the cache is controlled by the round-robin replacement algorithm. This
update may evict a valid line at that location.
6. Once the cache is updated, the eight valid bits of the fetch buffer are invalidated and the
cacheline valid bit is set.
4.2.4
Round-Robin Replacement Algorithm
The line replacement algorithm for the instruction cache is round-robin. Each set in the instruction
cache has a round-robin pointer that keeps track of the next line (in that set) to replace. The next
line to replace in a set is the one after the last line that was written from a fetch buffer. For example,
if the line for the last external instruction fetch was written into way 5-set 2, the next line to replace
for that set would be way 6. The other round-robin pointers for the other sets will not be affected.
After reset, way 31 is pointed to by the round-robin pointer for all the sets. Once a line is written
into way 31, the round-robin pointer points to the first available way of a set, beginning with way0
if no lines have been locked into that particular set. Locking lines into the instruction cache reduces
the available lines for cache updating. For example, if the first three lines of a set were locked
down, the round-robin pointer would point to the line at way 3 after it rolled over from way 31.
Refer to
Section 4.3.4, "Locking Instructions in the Instruction Cache" on page 4-6
on cache locking.
4.2.5
Parity Protection
The instruction cache is protected by parity to ensure data integrity. Each instruction cache word
has 1 parity bit. The instruction cache tag is not parity protected. When a parity error is detected on
an instruction cache access, a prefetch abort exception occurs if the Intel® XScale™ core attempts
to execute the instruction. Before servicing the exception, hardware places a notification of the
error in the Fault Status Register (Coprocessor 15, register 5).
A software exception handler can recover from an instruction cache parity error. This can be
accomplished by invalidating the instruction cache and the branch target buffer and then returning
to the instruction that caused the prefetch abort exception. A simplified code example is shown in
Example 4-1, Recovering from an Instruction Cache Parity
choose to invalidate the specific line that caused the exception and then invalidate the BTB.
Intel® XScale™ Microarchitecture User's Manual
Instruction Cache
for more details
Error. A more complex handler might
4-3
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