Table of Contents
Advertisement
Memory Management
This chapter describes the memory management unit implemented in the Intel® XScale™ core.
3.1
Overview
The Intel® XScale™ core implements the Memory Management Unit (MMU) Architecture
specified in the ARM Architecture Reference Manual. To accelerate virtual to physical address
translation, the Intel® XScale™ core uses both an instruction Translation Look-aside Buffer (TLB)
and a data TLB to cache the latest translations. Each TLB holds 32 entries and is fully-associative.
Not only do the TLBs contain the translated addresses, but also the access rights for memory
references.
If an instruction or data TLB miss occurs, a hardware translation-table-walking mechanism is
invoked to translate the virtual address to a physical address. Once translated, the physical address
is placed in the TLB along with the access rights and attributes of the page or section. These
translations can also be locked down in either TLB to guarantee the performance of critical
routines.
The Intel® XScale™ core allows system software to associate various attributes with regions of
memory:
•
Cacheable
•
Bufferable
•
Line allocate policy
•
Write policy
•
I/O
•
Mini Data Cache
•
Coalescing
See
Section 3.2.3, "Data Cache and Write Buffer" on page 3-2
and
Section 2.3.2, "New Page Attributes" on page 2-9
mapped in the MMU descriptors.
Note: The virtual address with which the TLBs are accessed may be remapped by the PID register. See
Section 7.2.11, "Register 13: Process ID" on page 7-12
3.2
Architecture Model
The following sub-sections describe the Architecture Model.
Intel® XScale™ Microarchitecture User's Manual
for a description of page attributes
to find out where these attributes have been
for a description of the PID register.
3
3-1
Advertisement
Table of Contents
