Terminology And Acronyms - Intel PXA255 User Manual

Xscale microarchitecture
Hide thumbs Also See for PXA255:
Table of Contents

Advertisement

Introduction
1.3.2

Terminology and Acronyms

ASSP
API
Assert
BTB
Clean
Coalescing
Deassert
Flush
NOP
Privilege Mode
Reserved
TLB
1-6
Application Specific Standard Product. Defined for a specific purpose
but not exclusively available to a single customer.
Application Programming Interface, typically a defined set of function
calls and passed parameters defining how layers of software interact.
This term refers to the logically active value of a signal or bit.
Branch Target Buffer, a predictor of instructions that follow branches.
A 'clean' operation with regard to a data cache is the writing back of
modified data to the external memory system, resulting in no 'dirty' lines
remaining in the cache.
Coalescing means bringing together a new store operation with an
existing store operation already issued. This includes, in Peripheral
Component Interconnect [PCI] terminology, write merging, write
collapsing, and write combining.
This term refers to the logically inactive value of a signal or bit.
A 'flush' operation invalidates the location(s) in the cache by deasserting
the valid bit. This now invalid cacheline will no longer be searched on
cache accesses. A 'flush' operation on a write-back data cache does not
implicitly imply a 'clean' operation.
Shortening of No OPeration, meaning an instruction with no state
changing effect. A typical example might be Add-constant-zero without
condition flag update
Any chip mode of operation that is not User Mode; the mode typically
used for applications software. A Privileged Mode gains access to shared
system resources.
A reserved field is a register field that may be used by an implementation
but not intended to be programmed. If the initial value of a reserved field
is supplied by software, this value must be zero. Software should not
modify reserved fields or depend on any values in reserved fields.
Translation Look-aside Buffer, a cache of Page Table descriptors loaded
from memory to minimize page-table walking overhead.
Intel® XScale™ Microarchitecture User's Manual

Advertisement

Table of Contents
loading

Table of Contents