Table of Contents
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Contents
1
Introduction...................................................................................................................................1-1
1.1
About This Document ........................................................................................................1-1
1.1.1
How to Read This Document ................................................................................1-1
1.1.2
Other Relevant Documents ..................................................................................1-1
1.2
Application Processors ......................................................................................................1-2
1.2.1
ARM* Compatibility ...............................................................................................1-3
1.2.2
Features................................................................................................................1-3
1.2.2.1
1.2.2.2
1.2.2.3
1.2.2.4
1.2.2.5
1.2.2.6
1.2.2.7
1.2.2.8
1.2.2.9
1.3
Terminology and Conventions ...........................................................................................1-6
1.3.1
Number Representation........................................................................................1-6
1.3.2
Terminology and Acronyms ..................................................................................1-6
2
Programming Model .....................................................................................................................2-1
2.1
ARM* Architecture Compatibility........................................................................................2-1
2.2
ARM* Architecture Implementation Options ......................................................................2-1
2.2.1
Big Endian versus Little Endian ............................................................................2-1
2.2.2
Thumb...................................................................................................................2-1
2.2.3
ARM* DSP-Enhanced Instruction Set...................................................................2-2
2.2.4
Base Register Update...........................................................................................2-2
2.3
Extensions to ARM* Architecture.......................................................................................2-2
2.3.1
DSP Coprocessor 0 (CP0)....................................................................................2-3
2.3.1.1
2.3.1.2
2.3.2
New Page Attributes .............................................................................................2-9
2.3.3
Additions to CP15 Functionality ..........................................................................2-10
2.3.4
Event Architecture ..............................................................................................2-11
2.3.4.1
2.3.4.2
2.3.4.3
2.3.4.4
2.3.4.5
2.3.4.6
3
Memory Management...................................................................................................................3-1
3.1
Overview ............................................................................................................................3-1
3.2
Architecture Model.............................................................................................................3-1
3.2.1
Version 4 vs. Version 5 .........................................................................................3-2
3.2.2
Instruction Cache ..................................................................................................3-2
3.2.3
Data Cache and Write Buffer ................................................................................3-2
Intel® XScale™ Microarchitecture User's Manual
Multiply/Accumulate (MAC)...................................................................1-3
Memory Management ...........................................................................1-4
Instruction Cache ..................................................................................1-4
Branch Target Buffer.............................................................................1-4
Data Cache ...........................................................................................1-4
Performance Monitoring........................................................................1-5
Power Management ..............................................................................1-5
Debug ...................................................................................................1-5
Multiply With Internal Accumulate Format ............................................2-3
Internal Accumulator Access Format ....................................................2-6
Exception Summary ............................................................................2-11
Event Priority.......................................................................................2-11
Prefetch Aborts ...................................................................................2-12
Data Aborts .........................................................................................2-12
Events from Preload Instructions ........................................................2-14
Debug Events .....................................................................................2-15
Contents
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