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2.3.2
New Page Attributes
The Intel® XScale™ core extends the ARM* page attributes defined by the C & B bits in the page
descriptors with an additional X bit. This bit allows four more attributes to be encoded when X=1.
These new encodings include allocating data for the mini-data cache and write-allocate caching. A
full description of the encodings can be found in
page
3-2.
The Intel® XScale™ core retains ARM* definitions of the C & B encoding when X = 0, which is
different than the StrongARM* products. The memory attribute for the mini-data cache has been
moved and replaced with the write-through caching attribute.
When write-allocate is enabled, a store operation that misses the data cache (cacheable data only)
will generate a line fill. If disabled, a line fill only occurs when a load operation misses the data
cache (cacheable data only).
Write-through caching causes all store operations to be written to memory, whether they are first
written to the cache or not. This feature is useful for maintaining data cache coherency.
The Intel® XScale™ core also adds a P bit in the first level descriptors to allow an ASSP to
identify a new memory attribute. The application processor doesn't implement a function for this
bit. All instances of the P bit in first-level descriptors must be written as zero. Bit 1 in the Control
Register (coprocessor 15, register 1, opcode=1) that is used to interact with the P bit must also be
written as zero.
The X, C, B & P attributes are programmed in the translation table descriptors, which are
highlighted in
Descriptors for Coarse Page Table" on page 2-9
Fine Page Table" on page
Intel® XScale™ core, one is used for the coarse page table and the other is used for the fine page
table.
AP bits are ARM* Access Permission controls.
Table 2-8. First-level Descriptors
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Section base address
Table 2-9. Second-level Descriptors for Coarse Page Table
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Intel® XScale™ Microarchitecture User's Manual
Table 2-8, "First-level Descriptors" on page
2-10. Two second-level descriptor formats have been defined for the
Coarse page table base address
Fine page table base address
Large page base address
Small page base address
Extended small page base address
Section 3.2.3, "Data Cache and Write Buffer" on
2-9,
Table 2-9, "Second-level
and
Table 2-10, "Second-level Descriptors for
SBZ
SBZ
TEX
AP
SBZ
SBZ
TEX
AP3
AP3
SBZ
Programming Model
8
7
6
5
4
3
2
1
0 0
P
Domain
SBZ
0 1
P
Domain
0 C B 1 0
P
Domain
SBZ
1 1
8
7
6
5
4
3
2
1
0 0
AP2
AP1
AP0
C B 0 1
AP2
AP1
AP0
C B 1 0
TEX
AP
C B 1 1
0
0
2-9
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