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Software Debug
The debug handler can be downloaded and locked directly into the instruction cache through the
JTAG interface so external memory is not required to contain debug handler code.
10.1.2
Monitor Mode
In monitor mode, debug exceptions are handled like ARM* prefetch aborts or ARM* data aborts,
depending on the cause of the exception.
When a debug exception occurs, the processor switches to abort mode and branches to a debug
handler using the pre-fetch abort vector or data abort vector. The debugger then communicates with
the debug handler to access processor state or memory contents.
10.2
Debug Registers
CP15 registers are accessible using MRC and MCR. CRn and CRm specify the register to access.
The opcode_1 and opcode_2 fields are not used and must be set to 0. Software access to all debug
registers must be done in privileged mode. User mode access will generate an undefined instruction
exception. Specifying registers which do not exist has unpredictable results.
Table 10-1. Coprocessor 15 Debug Registers
Instruction breakpoint register 0 (IBCR0)
Instruction breakpoint register 1 (IBCR1)
Data breakpoint register 0 (DBR0)
Data breakpoint register 1 (DBR1)
Data breakpoint control register (DBCON)
CP14 registers are accessible using MRC, MCR, LDC and STC (CDP to any CP14 registers will
cause an undefined instruction trap). The CRn field specifies the number of the register to access.
The CRm, opcode_1, and opcode_2 fields are not used and must be set to 0.
Table 10-2. Coprocessor 14 Debug Registers
TX Register (TX)
RX Register (RX)
Debug Control and Status Register (DCSR)
Trace Buffer Register (TBREG)
Checkpoint Register 0 (CHKPT0)
Checkpoint Register 1 (CHKPT1)
TXRX Control Register (TXRXCTRL)
The TX and RX registers, certain bits in the TXRXCTRL register, and certain bits in the DCSR can
be accessed by a debugger through the JTAG interface. This is to allow an external debugger to
have access to the internal state of the processor. For the details of which bits can be accessed see
Table
10-8,
10-2
Register name
Register name
Table 10-12
and
Table
10-3.
CRn
14
14
14
14
14
CRn
8
9
10
11
12
13
14
Intel® XScale™ Microarchitecture User's Manual
CRm
8
9
0
3
4
CRm
0
0
0
0
0
0
0
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