Software Debug Notes - Intel PXA255 User Manual

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Software Debug
10.15

Software Debug Notes

1) Trace buffer message count value on data aborts:
LDR to non-PC that aborts gets counted in the exception message. But an LDR to the PC that
aborts does not get counted as an exception message.
2) Software note on data abort generation in Special Debug State.
1) Avoid code that could generate precise data aborts.
2) If this cannot be done, then handler needs to be written such that a memory access is
followed by 1 NOP. In this case, certain memory operations must be avoided - LDM, STM,
STRD, LDC, SWP.
3) Data abort on Special Debug State:
When write-back is on for a memory access that causes a data abort, the base register is
updated with the write-back value. This is inconsistent with normal (non-SDS) behavior where
the base remains unchanged if write-back is on and a data abort occurs.
4) Trace Buffer wraps around and loses data in Halt Mode when configured for fill-once mode:
It is possible to overflow (and lose) data from the trace buffer in fill-once mode, in Halt Mode.
When the trace buffer fills up, it has space for 1 indirect branch message (5 bytes) and 1
exception message (1 byte).
If the trace buffer fills up with an indirect branch message and generates a trace buffer full
break at the same time as a data abort occurs, the data abort has higher priority, so the
processor first goes to the data abort handler. This data abort is placed into the trace buffer
without losing any data.
However, if another imprecise data abort is detected at the start of the data abort handler, it will
have higher priority than the trace buffer full break, so the processor will go back to the data
abort handler. This 2nd data abort also gets written into the trace buffer. This causes the trace
buffer to wrap-around and one trace buffer entry is lost (oldest entry is lost). Additional trace
buffer entries can be lost if imprecise data aborts continue to be detected before the processor
can handle the trace buffer full break (which will turn off the trace buffer).
This trace buffer overflow problem can be avoided by enabling vector traps on data aborts.
5) The TXRXCTRL.OV bit (overflow flag) does not get set during high-speed download when the
handler reads the RX register at the same time the debugger writes to it.
If the debugger writes to RX at the same time the handler reads from RX, the handler read
returns the newly written data and the previous data is lost. However, in this specific case, the
overflow flag does not get set, so the debugger is unaware that the download was not
successful.
10-46
Intel® XScale™ Microarchitecture User's Manual

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