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Programming Model
Table 2-4. MIAxy{<cond>} acc0, Rm, Rs
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Operation: if ConditionPassed(<cond>) then
Exceptions: none
Qualifiers Condition Code
Notes:
The MIAxy instruction performs one16-bit signed multiply and accumulates these to a single 40-
bit accumulator. x refers to either the upper half or lower half of register Rm (multiplicand) and y
refers to the upper or lower half of Rs (multiplier). A value of 0x1 will select bits [31:16] of the
register which is specified in the mnemonic as T (for top). A value of 0x0 will select bits [15:0] of
the register which is specified in the mnemonic as B (for bottom).
MIAxy does not support unsigned multiplication; all values in Rs and Rm will be interpreted as
signed data values.
The instruction is only executed if the condition specified in the instruction matches the condition
code status.
2.3.1.2
Internal Accumulator Access Format
The Intel® XScale™ core defines a new instruction format for accessing internal accumulators in
CP0.
Table 2-5, "Internal Accumulator Access Format" on page 2-7
into the coprocessor register transfer space.
The RdHi and RdLo fields allow up to 64 bits of data transfer between standard ARM* registers
and an internal accumulator. The acc field specifies 1 of 8 internal accumulators to transfer data to/
from. The Intel® XScale™ core implements a single 40-bit accumulator referred to as acc0; future
implementations can specify multiple internal accumulators of varying sizes.
2-6
1 1 1 0 0 0 1 0 1 1 x y
if (bit[17] == 0)
<operand1> = Rm[15:0]
else
<operand1> = Rm[31:16]
if (bit[16] == 0)
<operand2> = Rs[15:0]
else
<operand2> = Rs[31:16]
acc0[39:0] = sign_extend(<operand1> * <operand2>) + acc0[39:0]
No condition code flags are updated
Instruction timings can be found
in
Section 11.2.4, "Multiply Instruction Timings" on page
Specifying R15 for register Rs or Rm has unpredictable results.
acc0 is defined to be 0b000 on the Intel® XScale
8
Rs
0 0 0 0 0 0 0 1
TM
shows that the opcode falls
Intel® XScale™ Microarchitecture User's Manual
7
6
5
4
3
2
1
0
Rm
11-5.
™ core.
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